1. Field of the Invention
The present invention relates to an interface circuit for use in a semiconductor device. More preferably, the present invention relates to a small-amplitude signal interface circuit, such as a Stub Series Terminated Logic (SSTL).
2. Description of the Related Art
In recent years, as the operating speed of semiconductor devices is increased, a technique of transferring data with high speed to an external interface, such as a DDR SDRAM (Double Data Rate SDRAM) or the like, using a small-amplitude signal interface (e.g., an SSTL) and an input/output synchronization signal, is more often used.
FIG. 13 shows an exemplary interface, SSTL_2, which is a kind of SSTL described in the Joint Electron Device Engineering Council (JEDEC) Standard No. 8-9B (JESD8-9B). The interface circuit is connected between an information processing section (not shown) of a semiconductor device which is a VIN-side device and an external device (e.g., a DDR SDRAM) which is a VOUT-side device. The VOUT-side device is connected via a series resistor RS to a transmission channel. The VIN-side device comprises an input buffer gate, an output buffer gate, and a terminal resistor RT. One end of the terminal resistor RT is connected to the transmission channel, while the other end is connected to a voltage VTT (i.e., ½ of a supply voltage VDDQ).
When the VOUT-side device outputs a “1” level which is equal to the supply voltage VDDQ or a “0” level which is equal to a ground VSS, a “1” level which is lower than the supply voltage VDDQ or a “0” level which is higher than the ground VSS is supplied to the VIN-side input buffer gate due to the series resistor RS and the terminal resistor RT. In other words, a small-amplitude signal is supplied. Therefore, a differential amplification circuit including a current mirror load is widely used for the VIN-side input buffer gate.
The input buffer gate formed of the differential amplification circuit receives a small-amplitude signal VIN supplied to the VIN-side device. In the input buffer gate, the magnitude of the small-amplitude signal VIN is compared with the magnitude of a voltage VREF (i.e., ½ of the supply voltage VDDQ) to determine a “1/0” level.
In the differential amplification circuit, a through current flows all the time when it is in the active state. Therefore, power consumption is larger than that of input buffer gates formed of a Complementary MOS (CMOS) circuit, but can input a small-amplitude signal with high speed. Also, when the VOUT-side device does not output the “1/0” level (i.e., a high-impedance state (Hi-Z state)), the voltage of the transmission channel is settled to VDDQ×½ due to the terminal resistor RT.
On the other hand, a means for transmitting and receiving data to and from a DDR SDRAM or the like with high speed using an input/output synchronization signal is used. In this technique, when data is input or output, a sender-side device (e.g., a semiconductor device) supplies data in synchronization with an edge of an input/output synchronization signal DQS, while a receiver-side device (e.g., a DDR SDRAM) receives data in synchronization with an edge of a supplied input/output synchronization signal. Thereby, variations in delay between the data and the input/output synchronization signal are reduced, so that the data can be easily synchronized with the input/output synchronization signal irrespective of the distance between the sender and the receiver.
FIG. 14 is an exemplary timing chart of a write operation to a DDR SDRAM which is described in JEDEC Standard No.79D (JESD79D). In FIG. 14, “CK” indicates a clock, “/CK” indicates an inverted clock, and “COMMAND” collectively indicates commands, “Address” collectively indicates banks and addresses, “DQS” indicates an input/output synchronization signal, “DQ” indicates a data signal, and “DM” indicates a write data mask permission signal. When a write operation is performed with respect to the DDR SDRAM, the input/output synchronization signal DQS and the data signal DQ are output from the semiconductor device.
In cycle T0, the semiconductor device outputs a write command (Write), a write bank (Bw), and a write address (Cw).
Near cycle T1, the semiconductor device causes the input/output synchronization signal DQS to go to the “0” level. At some point in cycle T1, the semiconductor device outputs first write data D0 as the data signal DQ. Here, an interval from when the input/output synchronization signal DQS first goes to the “0” level to when the input/output synchronization signal DQS goes to the “1” level is referred to as a preamble.
At the beginning of cycle T2, the semiconductor device causes the input/output synchronization signal DQS to go from the “0” level to the “1” level, and the DDR SDRAM receives the write data D0 in synchronization with this timing. At some point in cycle T2, the semiconductor device outputs second write data D1 as the data signal DQ. At the beginning of cycle T3, the semiconductor device causes the input/output synchronization signal DQS to go from the “1” level to the “0” level, and the DDR SDRAM receives the write data D1 in synchronization with this timing.
Thus, the semiconductor device switches the “1/0” level of the input/output synchronization signal DQS every clock cycle and outputs the data signal DQ in synchronization with a rising edge and a falling edge of the input/output synchronization signal DQS and at some point therebetween.
When a predetermined number of data signals DQ (in FIG. 14, four pieces of write data D0, D1, D2 and D3) have been output, the semiconductor device suspends outputting of the input/output synchronization signal DQS in the next cycle T6 (i.e., the output of the input/output synchronization signal DQS is caused to go to a “Hi-Z state”). Here, an interval from when the input/output synchronization signal DQS most recently goes to the “0” level to when the input/output synchronization signal DQS goes to the “Hi-Z state” is referred to as a postamble.
FIG. 15 is an exemplary timing chart of a read operation from a DDR SDRAM described in the JEDEC Standard No.79D (JESD79D). In FIG. 15, “CK” indicates a clock, “/CK” indicates an inverted clock, “COMMAND” collectively indicates commands, “Address” collectively indicates banks and addresses, “DQS” indicates an input/output synchronization signal, and “DQ” indicates a data signal. During the read operation from the DDR SDRAM, the input/output synchronization signal DQS and the data signal DQ are output from the DDR SDRAM. Note that, here, a latency (a delay (in clock cycles) from when the DDR SDRAM receives a command to when the DDR SDRAM outputs data) is assumed to be “two cycles (CL=2)”.
In cycle T0, the semiconductor device outputs a read command (Read), a read bank (Br), and a read address (Cr).
Near cycle T2 (one cycle before the latency), the DDR SDRAM causes the input/output synchronization signal DQS to go to the “0” level. Here, an interval from when the input/output synchronization signal DQS first goes to the “0” level to when the input/output synchronization signal DQS goes to the “1” level is referred to as a preamble.
At the beginning of cycle T4 (after the latency), the DDR SDRAM causes the input/output synchronization signal DQS to go to the “1” level, and at the same time, outputs first read data D0 as the data signal DQ. At the beginning of cycle T5, the DDR SDRAM causes the input/output synchronization signal DQS to go to the “0” level, and at the same time, outputs second read data D1 as the data signal DQ.
Thus, the DDR SDRAM switches the “1/0” level of the input/output synchronization signal DQS every clock cycle and outputs the data signal DQ in synchronization with a rising edge and a falling edge of the input/output synchronization signal DQS.
When a predetermined number of data signals DQ (in FIG. 15, the four pieces of read data D0, D1, D2 and D3) have been output, the DDR SDRAM suspends outputting of the input/output synchronization signal DQS in the next cycle T8 (i.e., the output of the input/output synchronization signal DQS is caused to go to the “Hi-Z state”). Also, the DDR SDRAM causes the input/output synchronization signal DQS to go to the “Hi-Z state”, and at the same time, also causes the data signal DQ to go to the “Hi-Z state”. Here, an interval from when the input/output synchronization signal DQS most recently goes to the “0” level to when the input/output synchronization signal DQS goes to the “Hi-Z state” is referred to as a postamble.
Since the input/output synchronization signal DQS and the data DQ are transferred with high speed, a small-amplitude signal interface, such as an SSTL or the like, is typically provided for the semiconductor device and the DDR SDRAM. Also, the input/output synchronization signal DQS and the data DQ are both a bidirectional signal which can be output by both the semiconductor device and the DDR SDRAM. When none of the semiconductor device and the DDR SDRAM outputs the input/output synchronization signal DQS, the input/output synchronization signal DQS is in the “Hi-Z state”. Similarly, when none of the semiconductor device and the DDR SDRAM outputs the data signal DQ, the data signal DQ is in the “Hi-Z state”. Assuming that the interface is formed of an SSTL as shown in FIG. 13, when the input/output synchronization signal DQS goes to the “Hi-Z state”, a potential at the input of the input buffer gate is settled to “VDDQ×½” due to the terminal resistor RT.
In the SSTL_2 interface of FIG. 13, a differential amplification circuit is expected to be used as the input buffer gate. Differential amplification circuits can receive a small-amplitude signal with high speed, though a through current flows all the time in the active state, resulting in large power consumption. Also, in the SSTL_2 interface, a reference voltage VREF is required to determine the “1/0” level of the small-amplitude signal in addition to the supply voltage VDDQ. Further, differential amplification circuits are an analog circuit, so that a relatively large mounting area is required.
To solve these problems, it is contemplated that an input buffer gate (e.g., an input buffer gate formed of a CMOS circuit) other than differential amplification circuits is used. However, in the interface of FIG. 13, when the input/output synchronization signal DQS is in the “Hi-Z state”, the potential at the input of the input buffer gate is “VDDQ×½”, so that a through current flows through the input buffer gate. In CMOS circuits, when a through current continues to flow, a deterioration or a destruction occurs in the circuit. Therefore, it is not easy to replace the input buffer gate formed of a differential amplification circuit with an input buffer gate formed of a CMOS circuit.
Therefore, when an input buffer gate formed of a CMOS circuit is used, the terminal resistor RT needs to be eliminated from the interface circuit. With such a configuration, when a bidirectional signal (i.e., the input/output synchronization signal DQS and the data signal DQ) is not output from any of the semiconductor device and the DDR SDRAM, the potential of the transmission channel (i.e., the potential at the input/output terminal of the VOUT-side device and the potential at the input of the VIN-side input buffer gate) are not settled (i.e., “Hi-Z state”), so that the potential level is considerably unstable. In this case, the potential of the transmission channel easily varies due to noise or the like, so that the input buffer gate erroneously recognizes the potential variation due to noise as a change in the “1/0” level. In particular, since the input/output synchronization signal DQS controls reception of the data DQ using a rising edge and a falling edge thereof, if the “1/0” level of the input/output synchronization signal DQS is erroneously recognized in the input buffer gate, the data DQ cannot be received with correct timing, leading to an erroneous operation.
FIG. 16 shows an exemplary configuration of another interface circuit. This interface circuit has a configuration similar to that of FIG. 13, except that the terminal resistor RT of FIG. 13 is eliminated and an input buffer gate which is formed of a CMOS circuit is provided instead of the input buffer gate formed of a differential amplification circuit. The other parts are similar to those of FIG. 13.
FIG. 17 shows an exemplary timing chart of a read operation from a DDR SDRAM when the interface circuit of FIG. 16 is used. In FIG. 17, “CK” indicates a clock, “/CK” indicates an inverted clock, “COMMAND” collectively indicates commands, “Address” collectively indicates banks and addresses, “DQS” indicates an input/output synchronization signal, “DQSI” indicates a DQS input which is supplied from the interface circuit to the semiconductor device, and “DQ” indicates a data signal. When a read operation from the DDR SDRAM is performed, the input/output synchronization signal DQS and the data signal DQ are output from the semiconductor device. Note that it is here assumed that the latency is “two cycles”.
In cycle T0, the semiconductor device outputs a read command (Read), a read bank (Br), and a read address (Cr).
Near cycle T2 (one cycle before the latency), the DDR SDRAM causes the input/output synchronization signal DQS to go to the “0” level. Here, since the input/output synchronization signal DQS is in the “Hi-Z state” in cycles before cycle T2, the potential easily varies due to noise or the like. For example, if the level of the input/output synchronization signal DQS varies in cycle T1, a change in the “1/0” level occurs in the DQS input DQSI which is supplied via the interface circuit to the semiconductor device. In this case, the semiconductor device erroneously receives the data signal DQ in synchronization with this variation.
Thus, when an input buffer gate in a small-amplitude signal interface (e.g., an SSTL) is formed of a circuit other than differential amplification circuits, various problems arise, including circuit destruction due to a through current, an erroneous operation due to erroneous recognition of the “1/0” level, and the like.